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Assignors: VAN DER GOOT, MARCEL, PAUL, GAEL, EKANAYAKE, VIRANTHA, KELLY, CLINTON W., NIJSSEN, RAYMOND, MANOHAR, RAJIT Publication of US20110066873A1 publication Critical patent/US20110066873A1/en Application granted granted Critical Publication of US8301933B2 publication Critical patent/US8301933B2/en Assigned to HERCULES CAPITAL, INC., AS AGENT reassignment HERCULES CAPITAL, INC., AS AGENT SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.) Filing date Publication date Application filed by Achronix Semiconductor Corp filed Critical Achronix Semiconductor Corp Priority to US12/559,102 priority Critical patent/US8301933B2/en Assigned to ACHRONIX SEMICONDUCTOR CORPORATION reassignment ACHRONIX SEMICONDUCTOR CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Original Assignee Achronix Semiconductor Corp Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.) Kelly Virantha Ekanayake Gael Paul Raymond Nijssen Marcel Van der Goot Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.) Granted Application number US12/559,102 Other versions US8301933B2 Google Patents US20110066873A1 - Multi-clock asynchronous logic circuits Hence, it has been proven effective and highly successful in increasing the TDF test frequency to the highest operating clock domain frequency of the design.US20110066873A1 - Multi-clock asynchronous logic circuits In an experimental 200 M-transistor and 4-clock-domains test-chip netlist, this methodology is able to identify clock sources for all registers in five minutes time, and that processing time is negligible when compared to the TDF automatic test pattern generation (ATPG) time. It identifies all user registers in the design and recursively identifies the clock sources of those registers through intelligent net connectivity analysis. The methodology advocated in this paper aims to overcome this bottleneck by introducing an automated yet comprehensive approach to segregate and consolidate the various clock domains in any design for more effective TDF testing. Despite transition delay fault (TDF) tests providing reasonable coverage against DSM marginal defects, this methodology is hampered in designs with multiple clock domains where the lowest operating clock frequency becomes the dominant TDF testing frequency. With the rapid advancement of fab process technology into the nanometer node era, there is an increasing trend in the manifestation of deep submicron (DSM) marginal defects in integrated circuit (IC) fabrication.
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